Octopus
hardware.F90
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1!! Copyright (C) 2008 X. Andrade, 2024. A Buccheri.
2!!
3!! This program is free software; you can redistribute it and/or modify
4!! it under the terms of the GNU General Public License as published by
5!! the Free Software Foundation; either version 2, or (at your option)
6!! any later version.
7!!
8!! This program is distributed in the hope that it will be useful,
9!! but WITHOUT ANY WARRANTY; without even the implied warranty of
10!! MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
11!! GNU General Public License for more details.
12!!
13!! You should have received a copy of the GNU General Public License
14!! along with this program; if not, write to the Free Software
15!! Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston, MA
16!! 02110-1301, USA.
17!!
18module hardware_oct_m
19
20 implicit none
21 private
22 public :: &
26
28 type cache_t
29 integer :: size
30 integer :: line_size
31 end type cache_t
32
33 interface cache_t
34 module procedure cache_t_init
35 end interface cache_t
38 type hardware_t
39 type(cache_t) :: l1
40 type(cache_t) :: l2
41 integer :: dblock_size
42 integer :: zblock_size
43 integer :: sblock_size
44 integer :: cblock_size
45 contains
46 procedure :: init => hardware_init
47 end type hardware_t
49 ! Same as getting sizeof(a)
51 integer, public, parameter :: sizeof_real64 = 8
54 integer, public, parameter :: sizeof_complex64 = 16
55
57 integer, public, parameter :: sizeof_real32 = 4
58
60 integer, public, parameter :: sizeof_complex32 = 8
61
64
66 type(cache_t), public :: default_l1
67 type(cache_t), public :: default_l2
68
69contains
70
72 function cache_t_init(data_size, line_size) result(cache)
73 type(cache_t) :: cache
74 integer, intent(in) :: data_size
75 integer, intent(in) :: line_size
76
77 cache%size = data_size
78 cache%line_size = line_size
79
80 end function cache_t_init
81
82
83 ! TODO(Alex) Issue 1013. Change hardware class to a free function, and make cache_t instance global.
91 subroutine hardware_init(this, l1_cache, l2_cache)
92 class(hardware_t), intent(inout) :: this
93 type(cache_t), intent(in) :: l1_cache
94 type(cache_t), intent(in) :: l2_cache
95
96 integer, parameter :: cpu_default_states_per_block = 4
98 this%l1 = l1_cache
99 this%l2 = l2_cache
100
101 this%dblock_size = this%l1%size / (cpu_default_states_per_block * sizeof_real64)
102 this%dblock_size = this%dblock_size - mod(this%dblock_size, this%l1%line_size) - 2*this%l1%line_size
103
104 this%zblock_size = this%l1%size / (cpu_default_states_per_block * sizeof_complex64)
105 this%zblock_size = this%zblock_size - mod(this%zblock_size, this%l1%line_size) - 2*this%l1%line_size
106
107 this%sblock_size = this%l1%size / (cpu_default_states_per_block * sizeof_real32)
108 this%sblock_size = this%sblock_size - mod(this%sblock_size, this%l1%line_size) - 2*this%l1%line_size
109
110 this%cblock_size = this%l1%size / (cpu_default_states_per_block * sizeof_complex32)
111 this%cblock_size = this%cblock_size - mod(this%cblock_size, this%l1%line_size) - 2*this%l1%line_size
112
113 end subroutine hardware_init
114
115
116end module hardware_oct_m
117
118!! Local Variables:
119!! mode: f90
120!! coding: utf-8
121!! End:
subroutine hardware_init(this, l1_cache, l2_cache)
Initialise hardware object.
Definition: hardware.F90:98
type(hardware_t), public cpu_hardware
Global instance of CPU hardware specification.
Definition: hardware.F90:69
integer, parameter, public sizeof_real64
Number of bytes to store a variable of type real(real64)
Definition: hardware.F90:57
integer, parameter, public sizeof_real32
Number of bytes to store a variable of type real(real32)
Definition: hardware.F90:63
type(cache_t), public default_l2
Definition: hardware.F90:73
type(cache_t) function cache_t_init(data_size, line_size)
Initialise cache object.
Definition: hardware.F90:79
integer, parameter, public sizeof_complex64
Number of bytes to store a variable of type complex(real64)
Definition: hardware.F90:60
integer, parameter, public sizeof_complex32
Number of bytes to store a variable of type complex(real32)
Definition: hardware.F90:66
type(cache_t), public default_l1
Defaults covers common chip specification for (l1, l2) cache.
Definition: hardware.F90:72
Block-size optimisation for L1 cache size.
Definition: hardware.F90:44